Essentials of Professional VLSI Digital Design

  • VLSI

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 Become an advanced user of Verilog/System-Verilog Hardware Description Language: Learn the key language syntax and practical usage scenarios, enabling students to create a functioning digital design, simulate the design and understand gate-level implementation of the design by synthesis us

Course Objective:

Upon successful completion of the course, the student will:

(1) Have in-depth knowledge and reference examples on SystemVerilog coding constructs.

(2) Achieve deeper understanding of key aspects related to:

→  RTL coding considerations, 

    → Clock requirements

    → Clock-gating

    → Timing analysis

    → Reset

    → Synchronization

    → Finite State Machines

    → Power management

(3) Build sound awareness on the fundamentals of:

 Design for Test and Manufacturing (DFTM)

    → Power-Performance-Area (PPA) trade-offs

    → Bus Protocols and typical side-band signals

  → Industry standard IP MMR interfaces based on AMBA APB and AXI4-Lite protocols.

(4) Obtain an overview of key aspects related to:

→ Industry Standard IP and SOC design cycles

    → Gate Netlist generation flows

    → Physical design flows

(5) Understand how to systematically plan, partition, implement the RTL and create simple testbenches for simulating/debugging small-medium size IP designs.

(6) Gain confidence with basic IP design through implementation and touch-testing of a hierarchical IP with AMBA APB MMR programming interface and asynchronous clock domains.

(7) Gain sound familiarity with operating in a professional VLSI development environment that includes LINUX OS,usage of Perl programming for automation and ModelSim for simulations.

(8) Take away all the environment needed to conduct trial RTL implementation,  simulations, synthesis and schematic analysis on his/her personal machine using the lab reference material and free EDA tool** installs.

Who should go for this course?

Electronics Engineering graduate students with basic knowledge of digital design and some familiarity with Verilog coding, who want to explore the VLSI engineering field in detail, beyond the scope of their curriculum.

VLSI Masters students and Professionals entering the VLSI design and verification field, who want to build their career based up on a solid foundation of must-know concepts and good practices adopted by leading VLSI product companies.

VLSI enthusiasts who want to become self-sufficient with RTL coding and simulation using high quality reference/lab material and free EDA tools**.

Training Features:

1. Course Type

You will undergo self-paced learning where you will get an in-depth knowledge of various concepts that will be covered in the course.

2. Real-life Case Studies

Towards the end of the training, you will be working on a project where you will implement the techniques learnt during the course.

3. Assignments

Each class has practical assignments which shall be finished before the next class and helps you to apply the concepts taught during the class.

4. Lifetime Access

You get lifetime access to Learning Management System (LMS) where presentations, quizzes, installation guide & class recordings are there

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In Short

Instructor: Tony Thomas (B.Tech NIT Kerala, India, MBA Houston Baptist University Texas, USA) Tony Thomas has more than 20 years of experience in the semiconductor industry. His areas of expertize include IP and SOC front-end design, RTL coding and simulations, Electronic Design and Automation, device power management, system interconnect architecture and SPEC-to-GDSII SOC project execution.

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